This invention relates in general to semiconductor devices and more particularly to semiconductor devices including an electronic component, such as an integrated circuit, enclosed within a ceramic package.
In order to address packaging needs of high performance, very-large-scale-integration (VLSI) devices, semiconductor manufactures have largely adapted ceramic pin grid array (PGA) type packages for many VLSI applications. State of the art ceramic packaging offers good thermal conduction, relatively low thermal expansivity, and can be hermetically sealed. Improved thermal dissipation can be achieved by mounting the IC within the central cavity of the PGA package with the back side of the IC bonded to an upper surface of the cavity, which is known in the art as a cavity down configuration. The cavity down configuration allows a heat dissipation structure to be conveniently mounted to the upper surface of the PGA package. A cap is then hermetically sealed over the cavity. The package must be hermetically sealed to prevent moisture and contaminants from entering the package after assembly and corroding the package connections and contact pads on the IC enclosed with the package. The cap must be carefully sealed in place to provide maximal protection for the enclosed IC. Expansion and contraction of the package with ambient temperature changes over a period of time, as well as mechanical stress from handling and board placement, can result in a loss of the hermetic seal. A major disadvantage of the PGA package is that it is very expensive to produce and can represent a significant portion of the total cost of the packaged semiconductor device. As the IC integration level advances from VLSI to ultra-large-scale-integration (ULSI) ceramic packaging cost will consume an even greater portion of the total production cost.
The search for a low cost ceramic package led to the development of ceramic dual-inline-packages or "cerdip" packaging where ceramic powder is pressed to form a desired shape, then a standard leadframe is glass bonded to the pressed ceramic base. The cerdip package provides a low cost, hermetically sealed ceramic package, but the use of a conventional leadframe limits the number of leads available for connection to the IC. Other versions of cerdip packages are used with side brazed pins, however, these still lack the pin count necessary for high performance VLSI applications. Leadless chip carriers have been fabricated with ceramic material providing a high lead count alternative to cerdip packages, however, these packages are expensive to fabricate and thus do not provide a low cost ceramic package alternative. Despite the availability of low cost ceramic packaging in other formats, the PGA package remains the most widely used package format for high pin count VLSI applications.
Various approaches to addressing the problem of low cost PGA packaging meeting the requirements of hermeticity, strength and low thermal resistance for adequate heat dissipation are the subject of ongoing development within the semiconductor industry. Accordingly, a need existed for a packaged semiconductor device, in a low cost ceramic PGA format wherein the PGA package has a single-layer base and a hermetically sealed ceramic cap that is well seated to the package base.